Forum Discussion

AbhishekManoj's avatar
AbhishekManoj
Icon for New Contributor rankNew Contributor
5 months ago

Arria10 Pin Compatibility

Dear Team,

I'm using Arria10 SX SOM for my carrier card. I'm using 16 transceiver lanes for my data transfer.

I'm using bank 1E and 1F bank's each of four TXVR lanes for HDMI 2.1 signal.

Bank 1C and 1D for PCIe lanes. 2 TXVR lanes from 1C bank and 6 TXVR lanes from 1D bank for data transfer.

For PCIe signals for IC Bank I'm using the reference clock REFCLK_GXBL1C_CHB p&n from PCIe edge connectors and REFCLK_GXBL1C_CHT p&n coming from the clock synthesizer IC.

For ID bank REFCLK_GXBL1D_CHT P&N coming from the clock synthesizer IC.

Can you please confirm whether in which of the clock pin should I connect the clock coming from clock synthesizer and other clock coming from PCIe edge connector

Also please confirm for HDMI signals which pin REFCLK_GXBL1E_CHB or REFCLK_GXBL1E_CHT should I use for HDMI Rx clock coming from the re-driver IC or the clock coming from clock synthesizer IC.

Regards,

Abhishek

Fpga Devkit

4 Replies

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    4 months ago

    Hi Abhishek,

    Can you please confirm whether in which of the clock pin should I connect the clock coming from clock synthesizer and other clock coming from PCIe edge connector.

    >> You may refer Intel® Arria® 10 SoC Development Kit User Guide under page 82, there is suggested pin and signal name (let me know if i missunderstand your question)

    >>

    Also please confirm for HDMI signals which pin REFCLK_GXBL1E_CHB or REFCLK_GXBL1E_CHT should I use for HDMI Rx clock coming from the re-driver IC or the clock coming from clock synthesizer IC.

    >> Are you trying to connect PCie pin to the HDMI ? Or this is different project ? just trying to understand better

    >> I would assume the rx clock that you mention will be the rx cdr reference clock , (please correct me if I am wrong. )

    >> IF yes, it require free running clock

    >>separate fr_clk clock source is required (as stated in the A10 HDMI user guide) for all A10 HDMI designs.

    >>Also, I would suggest to refer to the design example for Arria 10 device https://www.intel.com/content/www/us/en/design-example/715141/arria-10-uhd-video-reference-design.html

    >>below shows one of the connection .v file from our example design , please take as a reference

    >>

    Regards,

    Wincent_Altera

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    4 months ago

    Hi ,


    Just try to follow up on this thread. Please let me know if there is anything unclear .

    I would happy to assist further.


    Regards,

    Wincent


  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    4 months ago

    Hi ,

    Just try to follow up on this thread. Please let me know if there is anything unclear .

    I would happy to assist further.

    Regards,

    Wincent

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    4 months ago

    Hi ,


    Given that we not receive any response from you near 14 days.

    I sincerely hope that you had fix the problem somewhere else, with that said, I will close the notification ring on my place.

    Please be understand that we are in full commitment to ensure your success,


    If you happen to came back, please do file a new thread, we will be there to support.


    Regards,

    Wincent