Forum Discussion

vivekt's avatar
vivekt
Icon for New Contributor rankNew Contributor
4 years ago

ARRIA10 GX-DDR4

I am designing a board with Arria10GX with DDR4 module. The input DDR4 Ref clock for the FPGA is LVDS (133.33MHZ) and is generated by a clock generator . However the pinout provided by the RTL...
Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,

In the Arria 10 GX FPGA development kit, the memory related connection are made to a connector. It can be connected to different types of memories like DDR3, DDR4, RLD3 etc. The reference design top is also not assigned with any IO standard in the qsf file.

Please refer

https://www.intel.com/content/www/us/en/programmable/documentation/sam1403483633377.html#sam1403481946777, Table 33 for the required voltages for different I/O standards.

As per the table, you can interface with a LVDS input signal only if VCCPT of the bank = 1.8V.


Regards