Arria 10: Warm Reset Error

Hi,

I am using Quartus 17.1 version. And for the above query which I posted, I read the manuals and did some changes in our I/O muxing. I configured Dedicated I/O bank UART as the debug UART and now console is showing output.But in the message DDR calibration is getting failed.

The uart console is showing following Error:

U-Boot 2014.10 (Sep 17 2019 - 15:11:16)

CPU : Altera SOCFPGA Arria 10 Platform

BOARD : Altera SOCFPGA Arria 10 Dev Kit

I2C: ready

DRAM: WARNING: Caches not enabled

SF: Read data capture delay calibrated to 1 (0 - 2)

SF: Detected N25Q1024A with page size 256 Bytes, erase size 4 KiB, total 128 MiB

FPGA: Early Release Succeeded.

SF: Detected N25Q1024A with page size 256 Bytes, erase size 4 KiB, total 128 MiBemif_reset interrupt acknowledged

emif_reset interrupt acknowledged

emif_reset interrupt acknowledged

Error: Could Not Calibrate SDRAM

DDRCAL: Failed

INFO : Skip relocation as SDRAM is non secure memory

Reserving 2048 Bytes for IRQ stack at: ffe3a6e8

DRAM : 0 Bytes

data abort

pc : [<ffe001cc>] lr : [<ffe02491>]

sp : ffe3fff0 ip : 00000016 fp : 00000001

r10: ffd02078 r9 : ffe3aee8 r8 : ffe00000

r7 : ffe1d3c4 r6 : 00000000 r5 : 00000000 r4 : ffeff000

r3 : ffe3afaf r2 : ffe40000 r1 : ffe3d000 r0 : ffe3aee8

Flags: nzcv IRQs on FIQs on Mode SVC_32

Resetting CPU ...

resetting ...

Could you please help with the error?

Thanks,

Priya