Forum Discussion
Occasional ContributorArria 10 SoC DevKit: Can I drive DB-9 RS-232 port from HPS UART0 ?
Hi,
I now have the HPS UART0 routed through the FPGA OK to the DB9 RS-232 port.
The UART_RS232 soft IP is not required in the FPGA.
My problem here was caused by the RS-232 PHY on the dev board operating in an auto-shutdown mode that meant that the external tx/rx loopback test I was attempting would never wake the PHY.
Thanks,
Paul
Occasional ContributorHi,
I now have the HPS UART0 routed through the FPGA OK to the DB9 RS-232 port.
The UART_RS232 soft IP is not required in the FPGA.
My problem here was caused by the RS-232 PHY on the dev board operating in an auto-shutdown mode that meant that the external tx/rx loopback test I was attempting would never wake the PHY.
Thanks,
Paul
GSagl1New Contributor
Hi,
How did you do this? What is FPGA OK? I have a design in my FPGA and I'm not using the HPS at all, and I want to use UART to send data to the design in the FPGA. Is this what you also did, and How?
I hope you can help me understand what's going on,
Gurol
- PHJ
Hi Gurol -
We configured the pinmux in the HPS to route UART0 via the FPGA:
/* UART0 routed via FPGA */
alt_write_word(ALT_PINMUX_FPGA_UART0_USEFPGA_ADDR, ALT_PINMUX_FPGA_UART0_USEFPGA_SEL_SET(1));
We configured the FPGA to route the HPS UART0 signals to the appropriate input/output pins of the A10 - we only used tx/rx as we were not using flow control.
Best Regards,
Paul
corestarContributor
Hello, I'm having a similar problem except I want to access the RS-232 via the DB-9 on J25. I see the TX line togging coming out of the FPGA but nothing shows up on the Teraterm on the PC. Works fine with JTAG UART, but that little window in the NIOS-II tools is really annoying.
Can you explain how you fixed the auto shutdown issue on the RS-232 Phy?
