Forum Discussion

RajanVaja's avatar
RajanVaja
Icon for New Contributor rankNew Contributor
2 years ago
Solved

Arria 10 SoC Development Kit: Not able to run Intel FPGA AI Suite Soc Design Example

I want to run "S2M Mode Demonstration Application" from Intel FPGA AI Suite Soc Design Example User Guide example on Arria 10 SoC Development Kit. I am using prebuilt images from $COREDLA_ROOT/demo/e...
Fpga Devkit
  • KianHinT_altera's avatar
    KianHinT_altera
    2 years ago

    Hi Rajan,

    Our factory apps team gotten back to me on this case and mentioned that the latest Arria 10 SoC rev E. boards have a slower SDRAM (BOM change) and they have already change the design example in 2024.1 AI FPGA Suite to be able to accommodate these boards as well as the previous versions of the FPGA AI Suite do not work on A10 SoC rev. E boards.

    Could you try on the design example in 2024.1 AI FPGA Suite?

    Thanks

    Regards

    Kian

KianHinT_altera's avatar
KianHinT_altera
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi Rajan,

Thanks for the reply and sorry for the delay, I'm still with checking with the owner of the design example on the configuration setup. Will let you know as soon as possible on this case.

Thanks

Regards

Kian

KianHinT_altera's avatar
KianHinT_altera
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi Rajan,

I'm sorry for the delay , didn't get a response yet from the AI suite team. Meanwhile I've a discussion on this case with my colleague and we are suspecting maybe still the DDR4 stability , it might be enough to boot but not stable to run the interference.

Does running the rocketboard (https://releases.rocketboards.org/2023.09/gsrd/a10_gsrd/sdimage.tar.gz,) passes the DDR4 BTS test but not the image that you're running for the interference test with DLA timeout? Is that the same memory settings per rocketboard?

Could I have a copy of your changes you made so that I could check the settings with the team ?

Thanks

Regards

Kian

  • RajanVaja's avatar
    RajanVaja
    Icon for New Contributor rankNew Contributor
    2 years ago

    Hi @khtan ,

    Thanks for the reply.

    We followed https://www.intel.com/content/www/us/en/docs/programmable/768979/2023-3-1/build-flow.html and created design. HPS was not booting in that. So on top of that we made changes in HPS DDR configuration as per GSRD. FPGA DDR configurations are same as per example design. We could not find Rocketboard design which has FPGA memory (it only has HPS memory) .

    As per my understanding, BTS needs specific sof to be loaded so we cannot use BTS with any custom design.