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antonkulya's avatar
antonkulya
Icon for New Contributor rankNew Contributor
4 years ago

Arria 10 power management

Is there are possibility to design the PCB with the Arria10 in such way that it is possible to shutdown the FPGA part while keeping the HPS running and being able to communicate with the HPS via Ethe...
EngWei_O_Intel's avatar
EngWei_O_Intel
Icon for Frequent Contributor rankFrequent Contributor
4 years ago

Hi Anton

For the HPS to be fully operational, the FPGA supply voltages monitored by the POR circuitry must be above their POR values. HPS is a Hard IP reside in FPGA and it needs to use the Periphery of FPGA to work.

There are options to clock gate the FPGA Fabric when they are not in use to reduce power which you can explore on this approach.

Thanks.

Eng Wei