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TSchu3's avatar
TSchu3
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Arria 10 Gx board, SFP connection no link

Hello all, I am attempting to bring up a link on a new Arria 10 Gx board, using the SFP+ connector. I started by generating an example design for the Low Latency Mac, with the 1G/2.5G Ethernet Example Design preset. This also generated a PHY, 1G/2.5G/5G/10G Multi Rate Ethernet PHY.

When I load this design on the board and connect it to a switch I can see 2.5G link lights. However, I cannot see a link established on the PHY port for LED_Link, I can also observe that rx_is_locked_to_data is constantly going up and down.
The Tx side is showing ready.
If I plug the cable in to a 1Gig switch I get no lights on the switch and the same results on the signal tap.
If I leave the cable unplugged I still see the same behavior on the signal tap.

I tried the included Board example design qts_com. which includes an SFP connection and I see the same behavior.

I don't have any idea what is going wrong here. I am sending in the correct Reference Clock to the example design of 125Mhz.

Any help troubleshooting this would be greatly appreciate.


Thank you!

Fpga Devkit

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  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    1 year ago

    Hi,


    Could you provide your current .qar file? So that I can have a look into the ip settings.


    Best regards,

    zying


  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    1 year ago

    Hi,

    How do I determine the current operating speed, not the default speed?

    >> In 10GBase-R MAC mode the MAC works with different speed just by repeating the same bit value for the duration of the speed. You can get the speed info from the input clock, as Phy line speed is aligned with the input clock.

    i.e., 1G output it repeats 10 cycles same bit value on the 10G link and there is change in the PHY line speed.

    Same is the case in 2.5G mode MAC manipulates the data to achieve 2.5G (4 clock cycles of same bit value and by reading the PHY speed it will result 10G but the MAC does the change in speed)

    Best regards,

    zying


    • TSchu3's avatar
      TSchu3
      Icon for Occasional Contributor rankOccasional Contributor
      1 year ago

      Thank you, this is very interesting. How does the MAC know that the data is/should be repeated and how often? the 'operating speed' signal is supposed to send this information to the MAC. If it always says 10G, then how would the MAC know it was really sending repeated 1G data, for example?

      Is this information stored somewhere in a MAC register?
      How can I gain access to it?



  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    1 year ago

    Hi,

    I will send the design for you as reference design through email. Our design team tested the A10 LL10G_Usxgmii_design on hardware in QPDS23.2 and the USXGMII is working for them.

    Channel 0: all speeds passed

    Please do let me know if you haven't received the email.

    Best regards,
    zying

  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    1 year ago

    Hi,


    Since no hear any feedback from you, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.


    Best regards,

    zying