Forum Discussion
AdzimZM_Altera
Regular Contributor
1 year agoHi Ram,
The example design should be able to support other clocks value.
If you are not sure about that, you can configure the EMIF IP setting with other clock value and run a compilation.
If the timing report shows that there is no issue with DDR timing, then the design should be okay.
I can suggest to run a DDR4 test with BTS application.
Also can you use latest Quartus release to run the test?
Regards,
Adzim