Forum Discussion
CHung
Occasional Contributor
Occasional ContributorAN881 reference design need to be upgraded for device 1SM21CH.
Hi, The following reference design is based on 1SM21BH device. https://fpgacloud.intel.com/devstore/platform/19.1.0/Pro/an881-pcie-avmm-dma-gen3x16-ddr4-and-hbm2/ We use Stratix 10 MX 1SM21C...
BoonT_Intel
Frequent Contributor
Frequent ContributorHi I am unable to get the waveform due to security reason. Can you please attach the screenshot here.
What you need to do is to capture the ltssmstate and lane_act signal to understand the Pcie issue
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_s10_pcie_avmm.pdf#page=80
CHungHi,
1. when reset is asserted:
2. reset is de-asserted
3. avmm_bridge_512_0 reset is de-asserted
4. idle
