Forum Discussion
SDavi9
Occasional Contributor
Occasional ContributorAltera\Intel Qsys DDR3 SDRAM Controller with UniPHY termination of RESET# pin
I am using the Altera Qsys DDR3 SDRAM Controller with UniPHY within a Cyclone V E device to interface to my DDR3 ! It states in the following DOC:- https://www.intel.com/content/dam/www/programmabl...
BoonT_Intel
Frequent Contributor
Frequent ContributorYes, it is not recommend to terminate the reset signal to any source include VTT
I am sorry to inform that the dev kit do not follow the recommendation. However, it is still functioning correctly. Please note that this is recommendation but not a hard rules.
