altera_reserved_tck hold timing violation
In the help document:
https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd10082012_359.html
it is mentioned to set altera_reserved_tck on global signal to avoid hold time violation,
but doing this give this error on quartus 19.3 arria 10:
Error: Peak virtual memory: 3362 megabytes
Error: Processing ended: Wed Jan 15 16:59:29 2020
Error: Elapsed time: 00:01:04
Error: System process ID: 55512
Error(13181): Source of port TCK in JTAG block auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|atom_inst|atom must be pin
Error(16297): An error has occurred while trying to initialize the plan stage.
Error: Quartus Prime Fitter was unsuccessful. 2 errors, 46 warnings
Error: Peak virtual memory: 3362 megabytes
Error: Processing ended: Wed Jan 15 16:59:29 2020
Error: Elapsed time: 00:01:04
Error: System process ID: 55512
Error(293001): Quartus Prime Full Compilation was unsuccessful. 4 errors, 1146 warnings
set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to altera_reserved_tck -entity Achilles_arria_X