Altera PCIE Dev Kit: Constant loss of data

Hello,

I use Altera Stratix II GX PCIE Development board and Jungo PCI Driver under Windows XP.

PCI IP Core + FIFO memory on FPGA compiled fine and works. I've tested with Jungo Windriver Demo application - DMA is working fine, all data is correct.

I'm trying to test DMA with Jungo Windriver application edited from Virtex5 sample.

DMA seems to be working (Interrupt method)

But the problem is that there is a constant loss of data.

Could you help me to find reason of this problem (data loss and noisy region)

Is it some kind of buffer overflow or (System / IP core) restrictions ?

I attach screenshot which shows problem.