Altera DE2 SDRAM Clock speed

I am sure the DE2 supports a max 100Mhz bus speed, i have done this with my last Nios Project

I had a SDRAM using the SOPC builder controller, flaking out at about 60 MHz, looked at the waveforms, looked at the Micron data sheets, inverted the "za_data <= zs_dq" register's clock (posedge to negedge), around line 665 in sdram.v and it miraculously runs over 100 MHz now.

In this moment, i use SDRAM with 143Mhz and the phase shift -3ns. Until now, I have no problem. You can try it.