Altera DE2 SDRAM Clock speed

I had a SDRAM using the SOPC builder controller, flaking out at about 60 MHz, looked at the waveforms, looked at the Micron data sheets, inverted the "za_data <= zs_dq" register's clock (posedge to negedge), around line 665 in sdram.v and it miraculously runs over 100 MHz now.