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Altera_Forum's avatar
Altera_Forum
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11 years ago

Altera Cyclone V development board FPGA problem (error code:-4)

I am working on the Altera Cyclone V Development board (revision D). It seems that the FPGA image is not loaded after power up. I found following lines in the uboot bootlog: reading soc_sy...
FBuss2's avatar
FBuss2
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7 years ago

I had the same problem. The reason was the wrong setting in the "Convert Prorgamming File" tool. When you add the SOF file, select the file, then click on "Properties" bottom right. Then click on "Compression". This is how it looks like in Quartus Prime 18.1.:

You also need to set the "Mode" to "Passive Parallel x16". Then save the soc_system.rbf file to the FAT partition on the SD card and u-boot can load it.

  • TOoi's avatar
    TOoi
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    7 years ago

    Thanks for the solution provided @FBuss2​ . Have been searching this error code for a while. I wish to add on something, the "Mode" is set according to the MSEL pin u set on the DE1-SoC board. You can refer to the table below, the table can be found in DE1-SoC User Manual provided by Terasic, section 3.1 Settings of FPGA Configuration Mode.