Forum Discussion

pankuolung's avatar
pankuolung
Icon for New Contributor rankNew Contributor
6 years ago

Altera 1588 FPGA solution

Hi there, Just found the Altera 1588 solution AN739 as the attached file and downloaded the reference design then try to run it. When I opened it using Quartus, It shows can't find the qip file as...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Av,


I presume you are the one that generated the data traffic and verified your own data traffic back in loopback mode,right ? Then you should have your design checking logic to read back and verify your streaming data.


I can tell you from TSE MAC side, we are using start of packet (SOP) and end of packet (EOD) signal to indicate the start and end of data packet flow.


So, you should have implemented your own design checking logic in your NIOS software as well.


Thanks.


Regards,

dlim


Recent Discussions