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Zhilang_X_Intel's avatar
Zhilang_X_Intel
Icon for New Contributor rankNew Contributor
5 years ago

Agilex F P-tile Debug Toolkit shows no DUT listed after design loaded

Issue Description: I enabled 'Debug Toolkit' feature of P-tile AVST PCIe Hard IP in Quartus and could see the PCIe endpoint in Linux, but No DUT listed in System Console after Load Design. Tried Qu...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

HI,


Do you see any other error message in debug toolkit ?


Also, have you done following as explained in P-tile user guide doc (page 164) ?

  • When you run a dynamically-generated design example on the Intel Development Kit, make sure that clock and reset signals are connected to their respective sources and appropriate pin assignments are made. Here are some sample .qsf assignments for the Debug Toolkit:
  • set_location_assignment PIN_A31 -to p0_hip_reconfig_clk_clk
  • set_location_assignment PIN_C23 -to xcvr_reconfig_clk_clk


The reconfig_clk should be around 100MHz to 125MHz.


Thanks.


Regards,

dlim


Zhilang_X_Intel's avatar
Zhilang_X_Intel
Icon for New Contributor rankNew Contributor
5 years ago

Hi dlim,

I do not see any errors in debug toolkit as blow:

As for the assignment, I assign a 100M clk to xcvr_reconfig_clk_clk, but for p0_hip_reconfig_clk_clk, I quartus assign it to 0 after platform designer generation as below:

I check the toolkit clk and reset signals as below: