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Zefu's avatar
Zefu
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2 years ago

Agilex 7 AGF027 FPGA 2x F-tile pcie IP system pll clock not working

Hello, We have an Intel Agilex 7 fpga dev kit from Intel, which features an AGFB027R24C FPGA (https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/agf027-and-agf023...
Board Debug
Fpga Devkit
RongY_altera's avatar
RongY_altera
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1 year ago

Hi Zefu,

We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum case, did not reach us as intended. As a result, we have a backlog of cases that we are currently working through.

Your upstream port is on bank 12C. You can generate an example design using Gen4 1x16 for this bank and try if host can recognize by lspci. Set PCIe speed in host BIOS to AUTO or Gen4.

Regards,

Rong