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Samo's avatar
Samo
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1 year ago

Agilex 5 reconfigurable PLL - emif

Trying to reconfig a PLL with the EMIF Calibration IP debug via system console Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs enabled dynamic config within IOPLL and included EMIT Calib...
Fpga Devkit
AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
3 months ago

Hi Lorenz,

 

For your issue, are you using the HSIO or HVIO I/O PLL block type?

 

Thanks.

LenzHyd's avatar
LenzHyd
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3 months ago

Hi,

we are using the calbus and EMIF calibration IP to reconfigure the PLL. Thus according to the Agilex 5 Clocking and PLL user guide, this shoud result in a HSIO I/O PLL block type. 

Thank you for your help.

Kind regards,
Lenz

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 months ago

    Hi Lenz,

     

    The minimum supported phase shift step is fixed by the VCO frequency (e.g., at 1 GHz VCO, the step is 125 ps). If the requested phase shift (e.g., 100 ps) does not align with this step size, the PLL cannot accurately deliver it.
     

    When multiple shifts are performed, quantization and rounding errors can accumulate, leading to some shifts being much larger than intended (i.e., the “occasional large jump” that you observed).
     

    Regards,

    Aqid