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Samo's avatar
Samo
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8 months ago

Agilex 5 reconfigurable PLL - emif

Trying to reconfig a PLL with the EMIF Calibration IP debug via system console Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs enabled dynamic config within IOPLL and included EMIT Calib...
Fpga Devkit
LenzHyd's avatar
LenzHyd
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10 hours ago

Hello Sir or Madam,

I have a similar problem. I am able to perform multiple phase shifts (more than seven), but some of them do not work properly.
To be more precise, most shifts behave as expected (roughly four out of five, although this is not entirely consistent), but occasionally the clock signal is shifted by much more than the intended 100 ps.

I would like to build a tapped delay line, and inconsistent phase shifts make this difficult.

I look forward to your reply.

Kind regards,
Lenz