Forum Discussion
Agilex 5 reconfigurable PLL - emif
Hello Sir or Madam,
I have a similar problem. I am able to perform multiple phase shifts (more than seven), but some of them do not work properly.
To be more precise, most shifts behave as expected (roughly four out of five, although this is not entirely consistent), but occasionally the clock signal is shifted by much more than the intended 100 ps.
I would like to build a tapped delay line, and inconsistent phase shifts make this difficult.
I look forward to your reply.
Kind regards,
Lenz
- AqidAyman_Altera3 months ago
Regular Contributor
Hi Lorenz,
For your issue, are you using the HSIO or HVIO I/O PLL block type?
Thanks.
- LenzHyd3 months ago
New Contributor
Hi,
we are using the calbus and EMIF calibration IP to reconfigure the PLL. Thus according to the Agilex 5 Clocking and PLL user guide, this shoud result in a HSIO I/O PLL block type.
Thank you for your help.
Kind regards,
Lenz- AqidAyman_Altera3 months ago
Regular Contributor
Hi Lenz,
The minimum supported phase shift step is fixed by the VCO frequency (e.g., at 1 GHz VCO, the step is 125 ps). If the requested phase shift (e.g., 100 ps) does not align with this step size, the PLL cannot accurately deliver it.
When multiple shifts are performed, quantization and rounding errors can accumulate, leading to some shifts being much larger than intended (i.e., the “occasional large jump” that you observed).
Regards,
Aqid