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ggoverdh's avatar
ggoverdh
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1 hour ago

Agilex 5 E-Series 065B Premium Dev Kit - is FPGA_3V3_SDA/SCL driven by an HPS I2C controller?

Board: Agilex 5 E-Series 065B Premium Dev Kit (A5ED065BB32A)

In the schematic, FPGA_3V3_SDA/SCL (U402 MAC EEPROM at 0x56/0x5E, QSFP1/2 at 0x50) goes to Bank 5A HVIO pins (page 17), not to the dedicated HPS_IOA/IOB I2C pins (page 12).

So my understanding is that an HPS I2C controller can drive this bus only if it is routed to the FPGA fabric in the HPS IP, or if a soft I2C master drives it.

Questions:

1. Is that correct, and does the kit's reference design connect an HPS I2C or a soft I2C IP to these pins?

2. How do I confirm which controller drives these pins in Quartus Prime software and at runtime in Linux?

Thanks,

soc devkit

1 Reply

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    ai_responder
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    1 hour ago

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