Agilex 5 E-Series 065B Premium Dev Kit - is FPGA_3V3_SDA/SCL driven by an HPS I2C controller?

Hello,

Please refer to my answer below:

1. Is that correct, and does the kit's reference design connect an HPS I2C or a soft I2C IP to these pins?

<ANS> The dev kit schematic confirms FPGA_3V3_SCL/SDA is the "QSFP1, QSFP2, and EEPROM I2C interface FPGA", meaning those signals are wired to FPGA fabric I/O, not to the dedicated HPS IOA/IOB pads. The published HPS baseline for this kit also does not connect an HPS I2C controller or a soft I2C master to those pins.

Reference: Agilex™ 5 FPGA E-Series 065B Premium Development Kit User Guide, https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium-065b/gsrd/ug-gsrd-agx5e-premium-065b/

2. How do I confirm which controller drives these pins in Quartus Prime software and at runtime in Linux?

<ANS> In Quartus Prime:

1. Search the QSF or Pin Planner for FPGA_3V3_SDA and FPGA_3V3_SCL. No location assignment means nothing in that project drives the bus.
2. In Platform Designer, open the HPS Pin Mux tab. If I2C0 or I2C1 is set to FPGA, follow i2c0_sda_i, i2c0_sda_oe, i2c0_scl_in_clk, and i2c0_clk_clk (or the I2C1 equivalents) to the top-level ports. Those conduits tied to the Bank 5A pins mean the HPS I2C controller is the master.
3. If a soft I2C IP has its SDA and SCL ports connected to those same pins, that IP is the master.

In Linux, on the board booted from that image, run i2cdetect -l. An enabled HPS I2C controller shows up as a DesignWare adapter (i2c_designware). A soft master shows up only when that fabric IP and its device-tree node are in the image. However, on the enablement baseline, neither adapter is attached to FPGA_3V3_SCL/FPGA_3V3_SDA. 

Thank you.