Agilex™ 5 FPGA E-Series 065B Modular Dev Kit PCIe design does not build after tool version upgrade

Upgrading the IP regenerates all of the QSYS and RTL files for the IP. It seems the example design was created by editing of RTL files generated by the tools. The edits are overwritten when the IP is regenerated. The edits need to be restored to the top level of the design:

examples\pcie_ed\pcie_ed_24p1\pcie_ed\synth\pcie_ed.v

The edits can be restored by copying the original file from the example over the regenerated file. One module will have changed name when regenerated though and this name needs to be corrected in the pcie_ed.v file. Find the module pcie_ed_altera_mm_interconnect_1920_4uhoqna in the pcie_ed.v file. This module name needs to match the new name. The correct name to use can be found in the RTL file name in this directory:

examples\pcie_ed\pcie_ed\pcie_ed\altera_mm_interconnect_1920\synth

The new file name changes the last few characters e.g. pcie_ed_altera_mm_interconnect_1920_k23lfcq