Occasional Contributor
Occasional ContributorHi BCT_Intel,
If so, that makes me to make sure the trace fo the data and clk between device and FPGA have better to be the same length. And if the skew on the data pin and clk pin of the FPGA is very small, quartus will adjust the trace delay between clk and data to satisfy the timing according the skew information when edge-alignment and centre-aligned. In addition, I see that if I chose the method which puts the input clk to pll to generate sample clk by compensatory mode, in this method, the delay from data and clk pin to reg is almost the same, how quartus ii adjust the trace delay between data and clk to satisfy the timing?
Best regards,
Lambert
Frequent ContributorIn this case, you may use the set_input_delay to the data signal to compensate its skew relationship with clock in.
