New Contributor
New ContributorHi,
It worked with nios, but now we would like to hook SPI core to PCIe memory map for direct command from host pc.
I figured out that the problem was with avmm addressing. I am trying to understand, since SPI core using 16 bits bus width, but AVMM from PCIe using 32 bits bus width ( or could be 256 bits bus width).
This caused the issue, I am trying to fix it.
Thanks for your answer!
New ContributorDid you manged to solve 3 wire spi core connection ?
New ContributorHung Lam,
I'm facing similar issues. I have an SPI core (3wire) connected to bar0 of a PCIe hard core in an Stratix IV FPGA. It looks as if data is hold back somewhere before being written through the avalon bus to the SPI controller. For example if I write a sequence of values to the CS register and read it back I always read the previous value ... then reading again I get the value written. I tried other components like memory blocks and one of our custom blocks on bar0 of the PCI bus and they work fine.
I noticed like you that the data bus of the core is 16 bit wide. Addressing it is only possible using the 32 bit addressing scheme meaning every register is on multiples of 4bytes (instead of 2 bytes) It looks - as you suggested - to be an integration issue of platform designers avalon component generation with this core.
Could you share your solution with us ?
Best regards
Hermann
