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JW1121's avatar
JW1121
Icon for New Contributor rankNew Contributor
5 years ago

A pulse occurs during MAX 10 update while power is on

Hi, While MAX10 FPGA is programmed during power on state I find a low pulse(~ns) (occurs for each output pin. Does anybody know how to fix this issue.
ShafiqY_Intel's avatar
ShafiqY_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi JW1121,

Have you tried to set the unused pins to tri-stated in Quartus?

Please refer to the following picture (go to Assignment --> Device..)

Regards,

Matt