Forum Discussion
Hi,
Please correct me if I am wrong, as I understand it, you have some inquiries related to the Transform Length supported by the FFT IP in V series devices. If yes, for your information, the V series FFT IP supports the 8192 length. You may refer to the "Table 8. Basic Parameters" of the FFT IP user guide for further details on the supported length settings.
For your information the "Table 3. Performance and Resource Utilization" in the user guide are showing some example of resource utilization for some configuration. It is not referring the supported transform length.
Regarding the storage required, it is recommended for you to run through Quartus compilation to tell on the resource utilization based on your specific configuration.
Regarding the devkit price, you might need to refer to the https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/all-development-kits.html for further details. Alternatively, you may check with your local sales for as well.
As for the connection between ADC and devkit, I believe this would be dependent on the connectors available on your chosen devkit and ADC card. You might need to cross check on the devkit and ADC card datasheet to decide the connection.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
- MLaus35 years ago
New Contributor
Hi, thank you for your information so far, I really appreciate that! I found an Eval Board (DE10 from Terasic with Intel Cyclone® V SE 5CSXFC6D6F31C6N device) which could fit for my requirements: • Dual-core ARM Cortex-A9 (HPS) • 110K programmable logic elements • 5,761 Kbits embedded memory • 6 fractional PLLs I think it has enough resources and LEs. Do you think that it is possible to do the 8192-FFT on this board? Thank you in advance, Best regards Max- CheepinC_altera5 years ago
Regular Contributor
Hi Max, By merely based on the existing resource utilization table in the user guide, there should be no issue to implement the 8192 point FFT with the CV device. However, I would recommend you to create simple test design with the same CV device and run through Fitter compilation to verify this. Please let me know if there is any concern. Thank you. Best regards, Chee Pin