4-bit Synchronous JK flip flop Counter Erratic

Thank you for your additional response. I'm not a total beginner to Quartus, but my experience has been with a much older version (Quartus II). So, pretend I'm a beginner and that will pretty well be true.

Spent some time running ModelSim as a separate tool to follow up on your suggestion, but the 500+ page manual was a bit daunting. The 80-page tutorial from Intel was not much more friendly. Then I found a random web post suggesting that ModelSim not be run as a separate tool but integrated into a Quartus project by selecting it as an EDA tool when creating a new project. Tried it and it launched ModelSim at end of compile, but still not quite there yet. Any suggestions on a good tutorial to get a quick start on using Quartus Prime Lite with ModelSim for the MAX 10 FPGAs?

Also, can you please help me understand how to create an sdc file and determine what the contents should be? It doesn't seem to be generated by ModelSim; I found one example in the DE10-Lite docs and it says the following:

# This .sdc file is created by Terasic Tool.

# Users are recommended to modify this file to match users logic.