Forum Discussion
JKobl1
New Contributor
New Contributor4-bit Synchronous JK flip flop Counter Erratic
See attached image. Built a simple 4-bit synchronous counter in Quartus Prime using 7473 chips. This works erratically on DE10-Lite board with standard MAX 10 FPGA. Expect synchronous counting, ...
It's very important to learn how to create timing constraints for an FPGA design. Start with this online training:
https://www.intel.com/content/www/us/en/programmable/support/training/course/odsw1115.html
For simulation, this should help:
https://www.intel.com/content/www/us/en/programmable/support/training/course/ouwsdbug.html
#iwork4intel
sstrell
Super Contributor
Super ContributorWhat's your clock speed? What does your .sdc file look like?
#iwork4intel
JKobl1Thank you for responding.
I believe the default clock speed for this board is 50 MHz and I've done nothing to change it. If you're asking about the SIMCLK input, that's a pushbutton on the DE10-Lite board that we're clocking very, very slowly.
I have no .sdc file in the project.
