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BAmar1's avatar
BAmar1
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6 years ago

25G debug on Stratix10 MX h-tile

I am try to test 1 lane 25G by PRBS test. I build sample design in "25G Ethernet intel FPGA IP" . when I run Transciver Toolkits I am always get "couldn't grab setting for channel TX./RX . I add o...
BAmar1's avatar
BAmar1
Icon for New Contributor rankNew Contributor
6 years ago

first thank you for support .

yes I create example design from IP GUI and suitable pinout to hardware .

I found that if I open the toolkit when the link partner up (send data) this problem not happened and I can works with the toolkits and with " Ethernet link inspector -Link Monitor". but, if I change the link partner state (down) during tool running the tools stuck. its look like CDR locked issue ,if its locked the tool work otherwise its not stable. again this not happened in 40G IP .

how we can overcome this problem ?