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BAmar1's avatar
BAmar1
Icon for New Contributor rankNew Contributor
6 years ago

25G debug on Stratix10 MX h-tile

I am try to test 1 lane 25G by PRBS test. I build sample design in "25G Ethernet intel FPGA IP" . when I run Transciver Toolkits I am always get "couldn't grab setting for channel TX./RX . I add o...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

Is the problem happen if you use the generate example design from the IP GUI, and run it in the hardware? See table 7, the example design allows you to start or stop the packet generator and also check the PHY status.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-dex-s10-25gbe.pdf

Besides you can also refer to the example design for the connection of the JTAG and master bridge, this is required for the link monitor.

Regards -SK