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BAmar1's avatar
BAmar1
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6 years ago

25G debug on Stratix10 MX h-tile

I am try to test 1 lane 25G by PRBS test. I build sample design in "25G Ethernet intel FPGA IP" . when I run Transciver Toolkits I am always get "couldn't grab setting for channel TX./RX . I add o...
BAmar1's avatar
BAmar1
Icon for New Contributor rankNew Contributor
6 years ago

I don't have ability to check good link with partner because its debug stage and I need to see that CDR locked on data first. I want to make Serial loopback" and checking CDR locked on data .

Yes I enabled the NPDME. without enabling the NPDME I open "Ethernet link inspector - Link Monitor" and I see with loopback the link detected, all clocks are detected and PLL locked. when I running the Link Monitor with partner (Snow Ridge) if I enable and disable loopback the monitor stop working.

The error "Couldn't grab .." appears also in 100G IP, and 25G IP when select more then one lane. in 40G IP its works good .

this happened on Quartus Pro 19.2 and 19.3