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BAmar1
New Contributor
New Contributor25G debug on Stratix10 MX h-tile
I am try to test 1 lane 25G by PRBS test. I build sample design in "25G Ethernet intel FPGA IP" . when I run Transciver Toolkits I am always get "couldn't grab setting for channel TX./RX . I add o...
SengKok_L_Intel
Regular Contributor
Regular ContributorHi,
Before use transceiver toolkits, does the example design working as per the link below? This can help to ensure if the clock frequency is all running fine.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-dex-s10-25gbe.pdf
Did you enabled the "Native PHY Debug Master Endpoint"?
Regards -SK
