Forum Discussion
BQi
Occasional Contributor
Occasional Contributor20 10GE example design
The customer need 20 10GE in Stratix 10 MX 1SM16B, we use the 10GE low latency 10GE MAC example design. we found it has the parameter NUM_CHANNELS in hdl code the parameter NUM_CHANNELS would be fro...
Deshi_Intel
Regular Contributor
Regular ContributorHI,
In general, you can check out all Ethernet IP solution supported by Intel FPGA in below link.
- https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/ethernet-support.html
As you can see from above link - Etile Ethernet IP is called "E-Tile Hard IP for Ethernet"
- https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-s10-etile-hip-ethernet.pdf
- One IP can be configured to support max till 4 channels.
- Also, just curious why does customer wants to use Etile if customer is just targeting 10G application while Etile is meant to support till 56G ?
And also to address your concern better, Intel also developed an excel tool called Ethernet pin placement tool to guide user on how to fit IP solution into one Etile. Different setting selection like RSFEC and PTP will affect Etile pin placement accordingly.
- You can download Etile pin placement tool from below link -> Design flow and IP integration -> Etile channel placement tool
- https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/xcvr-phy-support.html
Thanks.
Regards,
dlim
BQiI have setup the 4 channels 10GE with the E tile hard IP for ethernet, I found 4 channel 10GE would cost less than 8K ALM, 3 M20K I don’t know if it is accurate resource utilization. I found the rough resource is 2.2K ALM, 6 M20K in table 7 of https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-s10-etile-hip-ethernet.pdf How about this ? And how to do 20+ 10GE with one E tile?
