1GHz clocks with 33% duty cycle

I'm looking for an FPGA that can generate high frequency clock signals(1GHz or more) with 33% duty cycle. I tried using Cyclone V SOC for this using PLLs but at 1GHz, 33% duty cycle is not possible.

Please let me know if there is a better FPGA solution(preferably and eval board). The main issue is that most FPGAs do support 1GHz clock frequencies but they all are at 50% duty cycles. Getting variable duty cycles is hard.

Secondly, I will need 3 such clock signal outputs with each having a variable phase shift.