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NZhan1
Occasional Contributor
Occasional Contributor两次编译收发器产生不同现象，但时序分析都是过的
Hi 有个比较奇怪的现象，Q17.1.2Pro编译出来的A.jic,下载到12块A10板卡上，有一块板子的1G/10GbE and 10Gbase-KR PHY的TX通道测试没有发出数据，而位于同一个PHY的RX通道却是正常的。工程里根据参考设计做了时序约束，只有几条时序违例：JTAG的相关时钟，FPGA给光模块disable信号，link引出的指示灯信号。 再次编译出B.jic，下进去就没...
NZhan1Occasional Contributor
Occasional ContributorHi Chee
Since I can’t login the Forum right now. So I send the top sdc to your personal email.
And currently, customer upgrade the project to 18.1Pro, and the tx failure issue occurs everytime after rerun compilation. And the TX failure issue happens on many other boards.
It is not just on one board now.
There are some changes of timing constrains requirements between 17.1pro and 18.1pro. will these be the reason of TX failure?
Thanks!
Regards，
Nicole
CheepinC_altera
Regular Contributor
Regular ContributorHi,
For your information, due to the change in the observation, it is rather difficult to tell what might be wrong. Please help to perform the debug items as in my previous note. You may want to prioritize the serial loopback and the simple native PHY design testing. Also, would you mind to elaborate if our customer is using oscilloscope to check on the TX output signal? If not, how did they check the signal when they are referring to no output.
Thank you.
Best regards,
Chee Pin
