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NZhan1
Occasional Contributor
Occasional Contributor两次编译收发器产生不同现象，但时序分析都是过的
Hi 有个比较奇怪的现象，Q17.1.2Pro编译出来的A.jic,下载到12块A10板卡上，有一块板子的1G/10GbE and 10Gbase-KR PHY的TX通道测试没有发出数据，而位于同一个PHY的RX通道却是正常的。工程里根据参考设计做了时序约束，只有几条时序违例：JTAG的相关时钟，FPGA给光模块disable信号，link引出的指示灯信号。 再次编译出B.jic，下进去就没...
NZhan1Occasional Contributor
Occasional ContributorHi Chee
Thanks for your suggestions!
For 4, there is no timing violation on these two clocks. How can I check tx_clkout and tx_pma_clkout to see if there is any valid clock and what is the frequency? Use a pin out?
Thanks!
Regards，
Nicole
CheepinC_altera
Regular Contributor
Regular ContributorHi,
You can tap these signals using signaltap or route the signals to an output pin and monitor at the oscilloscope. In signaltap, we are trying to see if there is any clock signal activities. With scope, we can verify the signal as well as if it is of the right frequency. Generally when the clkout is having correct frequency, the TX should be working.
Thank you.
Best regards,
Chee Pin
