Occasional Contributor
Regular ContributorHi,
As I understand it, you observe that by using A.jic into 12 A10 boards, one of the board's TX has no output. However, when you generate a new B.jic and download into the previously failing board, the TX is working fine.
Please see my comments as following:
1. Just would like to check with you if the B.jic generation involved recompilation of design?
2. If new compilation took place, the routing and timing of the design might be different as this is a new compilation, even though the SDC constraints remain the same. This could explain why you are observing differently between compilation.
3. Specific to the XCVR PHY, for your information, generally you would only need to constrain the top level input clocks as start. The PHY would have SDC to take care of the internal constraints. If you observe timing violation related to the other top level ports, you may then slowly constrain from there.
4. Just wonder if you have had a chance to try with the latest Quartus version ie 20.1? Just to ensure you are using the latest version with the most bug fixed.
Please feel free to let me know if you would require timing expert to further assist on the timing constraint of your design.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
Occasional Contributor
