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User1582192733150209's avatar
User1582192733150209
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5 years ago

Which part of design example eth_e2e_e10 based on platform designer

Hello Sir?Madam ​ I am running the eth_e2e_e10 design example now. I have a IP upgrading issue now . When I open the Quartus pro GUI in linux, and open the dcd.qpf project , system reminder to u...
User1582192733150209's avatar
User1582192733150209
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Some update , when I click the button Auto upgrade,Quartus printed below error information,any other way I can use to upgrade these IP if I can not open the qsys platform designer? thanks

Error: 2020.03.16.11:11:48 Error: Generation for Standard System (.qsys) files is not available in Pro, you can upgrade these files to Pro by opening them in Platform Designer for Quartus Pro.

Error: Quartus Prime Shell was unsuccessful. 15 errors, 0 warnings

Error: Peak virtual memory: 822 megabytes

Error: Processing ended: Mon Mar 16 11:12:26 2020

Error: Elapsed time: 00:00:50

Error: Total CPU time (on all processors): 00:02:00

Error(14923): Error upgrading Platform Designer file "../../hw/rtl/e10/fifo_scfifo/sc_fifo.qsys"

Error: 2020.03.16.11:12:14 Error: address_decode.rx_xcvr_half_clk.clk_in: rx_xcvr_half_clk.clk_in must be connected to a clock output

Error: 2020.03.16.11:12:14 Error: address_decode.rx_xcvr_half_clk.clk_in_reset: rx_xcvr_half_clk.clk_in_reset must be connected to a reset source

Error: 2020.03.16.11:12:14 Error: qsys-generate failed with exit code 3: 2 Errors, 0 Warnings

Error: 2020.03.16.11:12:16 Error: address_decode.rx_xcvr_half_clk.clk_in: rx_xcvr_half_clk.clk_in must be connected to a clock output

Error: 2020.03.16.11:12:16 Error: address_decode.rx_xcvr_half_clk.clk_in_reset: rx_xcvr_half_clk.clk_in_reset must be connected to a reset source

Error: 2020.03.16.11:12:16 Error: qsys-generate failed with exit code 3: 2 Errors, 0 Warnings

Error: 2020.03.16.11:12:17 Error: address_decode.rx_xcvr_half_clk.clk_in: rx_xcvr_half_clk.clk_in must be connected to a clock output

Error: 2020.03.16.11:12:17 Error: address_decode.rx_xcvr_half_clk.clk_in_reset: rx_xcvr_half_clk.clk_in_reset must be connected to a reset source

Error: 2020.03.16.11:12:17 Error: qsys-generate failed with exit code 3: 2 Errors, 0 Warnings

Error(14923): Error upgrading Platform Designer file "../../hw/rtl/e10/address_decoder/address_decode.qsys"

Error(11133): IP component QsysPrimePro with file "../../hw/rtl/e10/fifo_scfifo/sc_fifo.qsys" upgrade failed

Error(11133): IP component QsysPrimePro with file "../../hw/rtl/e10/address_decoder/address_decode.qsys" upgrade failed

Error(23031): Evaluation of Tcl script /root/inteldevstack/intelFPGA_pro/quartus/common/tcl/internal/ip_regen/ip_regen.tcl unsuccessful