Forum Discussion
Liyen
New Contributor
2 years agoHello,
To follow up my own question posted several days ago, I am trying to create a HLS design upon
Cyclone V soc (with dual arm cortex A9), it's clear that I can develop HLS IP components to optimize
system bottleneck, I would also like the entire design to be run on this soc so ability to communicate
between processor core(s) to HLS IP(s) is critical, would you anyone please guide me how to and/or
point me the appropriate online design documents? much appreciate
-liyen-