Forum Discussion
New ContributorWeird memory usage on fpga
Hi,
The 8 GB you're talking about is the global memory size, and that doesn't seem to be the problem here. The problem is that you are exceeding the on-chip BRAM blocks available on your FPGA, which is not 8 GB. Assuming that you are using an Arria 10 or Stratix 10 device, the BRAM is an order of Mega Bytes and way less than 8 GB In addition, you also have much more DSP usage and not just memory. When I saw your code, you had excessive loop unrolling in the design exceeding your hardware usage. Your loops over "P" or "M" like this one (for (int jway = 0; jway < P; jway++) ) cannot be fully unrolled for your FPGA device. Fully unrolling this loop means you need 4096 instances of this loop in parallel, replicating all the loop body, including memory and DSP. For instance, a floating point multiplication within this loop will require 4096 DSP slices for this single unrolling. But you have several full-unrolled loops.
Also, the compiler may implement a cache for your memory accesses using BRAM blocks. Your unrolling might explode the memory usage as well.
You need to specify your unrolling factor and tune it so that the design can fit into the FPGA device. You can remove all the unrolling first to see how it fits, and then optimize your design by tuning the unrolling factor.
Best regards,
Daouda
New ContributorI just get a warning that it is using more the max capacity of RAM. I get an error if I remove the -Xsdont-error-if-large-area-est flag. Here is a picture of the area estimation from the report. I have also done some calculations on it, and with the 8 GB of RAM it should be able to host all the three matrices in its largest forms. 4 byte floats x 4096^2 elements x 3 matrices = 402653184 Bytes < 8 GB, so I don't get why the reports says I'm using 264 GB of RAM.
Occasional ContributorHi,
The 8 GB you're talking about is the global memory size, and that doesn't seem to be the problem here. The problem is that you are exceeding the on-chip BRAM blocks available on your FPGA, which is not 8 GB. Assuming that you are using an Arria 10 or Stratix 10 device, the BRAM is an order of Mega Bytes and way less than 8 GB In addition, you also have much more DSP usage and not just memory. When I saw your code, you had excessive loop unrolling in the design exceeding your hardware usage. Your loops over "P" or "M" like this one (for (int jway = 0; jway < P; jway++) ) cannot be fully unrolled for your FPGA device. Fully unrolling this loop means you need 4096 instances of this loop in parallel, replicating all the loop body, including memory and DSP. For instance, a floating point multiplication within this loop will require 4096 DSP slices for this single unrolling. But you have several full-unrolled loops.
Also, the compiler may implement a cache for your memory accesses using BRAM blocks. Your unrolling might explode the memory usage as well.
You need to specify your unrolling factor and tune it so that the design can fit into the FPGA device. You can remove all the unrolling first to see how it fits, and then optimize your design by tuning the unrolling factor.
Best regards,
Daouda
- murrtank
Thank you!
