Forum Discussion

New Contributor

5 years ago

Using PLLs and FIFOs with AFU for Arria 10 PAC

Hello, I had a design that I was running on an FPGA (Cyclone V), which included a PLL and several FIFOs. I am trying to move the design to Arria 10 PAC. However, I don't know how to instantiate P...

EricMunYew_C_Intel

Frequent Contributor

5 years ago

Hi, Dina

Are you referring to a document for AFU for adding PLL and FIFO ? can point me to it ?

Eric

DMAHM1

New Contributor

5 years ago

For the question about adding FIFOs, I figured this out. For the PLL, this is the document I am referring to: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-afu-dev.pdf
It only explains how to get two different clock frequencies for the AFU. I guess I wanted to know if it was possible to have a shifted clock, too or not? I tried instantiating a PLL but it didn't work.

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Using PLLs and FIFOs with AFU for Arria 10 PAC

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