Forum Discussion
JButt5
New Contributor
New ContributorUnexpected low Kernel Clock Frequency
I'm working on an OpenCL kernel targeting a Cyclone V SoC that should process a continuous real-time sample stream at a sample rate of 16 MHz, which requires a certain kernel clock frequency so that ...
You seem to be using a custom-made BSP with multiple custom I/O channels; your critical path very likely lies in your BSP. You can try compiling an empty OpenCL kernel to see what operating frequency you will get. If what you get is still in the same range, then your critical path is in the BSP and you should optimize your BSP.
MEIYAN_L_Intel
Frequent Contributor
Frequent ContributorHi,
You can review Fmax information as in chapter 2.3.2 as link below:
The Fmax II report provides key performance metrics on all blocks including scheduled
fmax, sustainable II, block latency, and maximum interleaving iterations.
You can go though the best practice document as the link mentioned above and usually loop or memory usage having more impact on Fmax.
Thanks.
