Understanding Avalon-MM master in HLS generated code.
Hello,
I'm implementing a system using HLS that has a number of on-chip memories (currently 12, but it could increase) that need to be initialized from the host, with different data widths and address widths. I'm defining those memories as Avalon-MM slaves in their respective components, and then in a separate component have an Avalon streaming interface that is supposed to receive data from the host and populate the memories using a number of Avalon-MM master interfaces.
My question is, when I compile the HLS code and view the result in Platform Designer, the Avalon-MM master arguments are translated into two arguments, one with Avalon-MM master type which is named avmm_<number>_rw, and another one which is a conduit with the name of the argument as specified in the C++ code. What is this conduit argument and what am I supposed to connect it to?
Thanks in advance for your help.