Timing Analysis not met on holdtime

“FPGA_CLOCK_25MHZ” is the 25MHZ input clock， “pll_clk_out_50 ” is clock generated by PLL IP which is 50MHz, and “pll_clk_out_50 ” didn't meet the Timing analysis.

Hi,

Can you provide the design for investigation? May I know the software editon and version?

Thanks.

quartus prime standard 18.1。 While the design can't be shared for confidential reason.

Hope you could provide solutions to improve negative hold time slack. The setup time slack is ok.

Thanks!

Hi,

It is difficult to investigate the timing violation without the design. Can you report the failing path in details for both setup and hold?

Thanks.

How to see failing path in details for both setup and hold? I don't know how to get the failing path, how to operate to get it? Thanks!

Hi,

You may report setup summary > report timing on the failing clock > export the report

Thanks.

Hi,

You may right click on the failing clock > Report Timing

Thanks.

Hi,

May I know where do you want to find acq_trigger_in_reg[2], in RTL Viewer, Chip Planner, Timing Analyzer, or others?

It is difficult to improve the slack without looking into the design. May I request the timing report for the failing path in details?

Thanks.

Please check the report attached