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ljian50's avatar
ljian50
Icon for New Contributor rankNew Contributor
5 years ago

Time voilate with GPIO/DDIO in Arria 10

I have 8 groups 64 lines LVDS input, and 3 group of them received with GPIO, 5 group received with SERDES IP, but setup and hold time is not satisfyied
ShafiqY_Intel's avatar
ShafiqY_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi ljian50,

When you say "setup and hold time is not satisfied", can you elaborate more?

How much you get for setup and hold time?

Thanks

xytech's avatar
xytech
Icon for Contributor rankContributor
5 years ago

@ShafiqY_Intel​

Hi ,I am a colleague of ljian50, pls see AFE5809 datasheet section 7.10 and 8.3.8 for LVDS time requirements. （https://www.ti.com.cn/lit/ds/symlink/afe5809.pdf?ts=1591957198622&ref_url=https%253A%252F%252Fwww.ti.com.cn%252Fproduct%252Fcn%252FAFE5809）

We heard that A10 IC have some problem related to silicon and can not close the timing for DDIO, but not sure if this is true.

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@KhaiY_Intel​ I noticed you answered on a similar question some months ago, would you pls also help take a look on this question? Thanks!

https://forums.intel.com/s/question/0D50P00004Q8inFSAR/using-ddioin-to-read-adc-data-and-timing-analysis

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