Forum Discussion

ljian50's avatar
ljian50
Icon for New Contributor rankNew Contributor
6 years ago

Time voilate with GPIO/DDIO in Arria 10

I have 8 groups 64 lines LVDS input, and 3 group of them received with GPIO, 5 group received with SERDES IP, but setup and hold time is not satisfyied
ShafiqY_Intel's avatar
ShafiqY_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hi ljian50,

When you say "setup and hold time is not satisfied", can you elaborate more?

How much you get for setup and hold time?

Thanks

ljian50's avatar
ljian50
Icon for New Contributor rankNew Contributor
6 years ago

If DDIO sample with the input clock from pin, and I change the data time delay from pin to DDIO input use INPUT_DELAY_CHAIN in .QSF file, hold time is never satisfied. The result is below