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ljian50's avatar
ljian50
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6 years ago

Time voilate with GPIO/DDIO in Arria 10

I have 8 groups 64 lines LVDS input, and 3 group of them received with GPIO, 5 group received with SERDES IP, but setup and hold time is not satisfyied
ShafiqY_Intel's avatar
ShafiqY_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hi ljian50,

When you say "setup and hold time is not satisfied", can you elaborate more?

How much you get for setup and hold time?

Thanks

ljian50's avatar
ljian50
Icon for New Contributor rankNew Contributor
6 years ago

This is one time run result. I use PLL phase in SDC file to adjust the timing result, but never succed. Hold time even is larger than 3.571ns(280MHz). I don't know how to satisfy the timing . Is there anything else i forget to do with my SDC file?