Forum Discussion
SBioo
Occasional Contributor
Occasional ContributorSuper Long Compilation Time
I've designed a code in OpenCL, targeting Arria 10 FPGAs. In my design, I have specified parameters that control the size of the mode, with respect to the level of parallelism. As I grow this paramet...
SBiooOccasional Contributor
Occasional ContributorA follow up question. Based on what you said, should I conclude that my design is consuming much larger resources compared to what is being reported? Or we are suffering from something like fan-out problem.
HRZ
Frequent Contributor
Frequent ContributorIf it is stuck during fitting, the problem is likely due to high resource usage. Fan-out issues usually cause trouble during routing.
