Forum Discussion
SBioo
Occasional Contributor
Occasional ContributorSuper Long Compilation Time
I've designed a code in OpenCL, targeting Arria 10 FPGAs. In my design, I have specified parameters that control the size of the mode, with respect to the level of parallelism. As I grow this paramet...
HRZ
Frequent Contributor
Frequent ContributorThe estimation of the compilation report is not very reliable. Any compilation on Arria 10 that does not finish within 24 hours will likely never finish. You should be able to use all the DSPs and ~90% of the Block RAMs on Arria 10 without any fitting/routing failures. However, the story would be quite different with respect to logic; anything beyond 80% logic utilization will likely fail to fit or route.
SBiooOccasional Contributor
Occasional ContributorA follow up question. Based on what you said, should I conclude that my design is consuming much larger resources compared to what is being reported? Or we are suffering from something like fan-out problem.
- HRZ
If it is stuck during fitting, the problem is likely due to high resource usage. Fan-out issues usually cause trouble during routing.
